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Accueil > Thèses et HDR > Thèses en 2015

12/06/2015 - Thomas SOUVIGNET

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Thomas SOUVIGNET soutient sa thèse le 12 juin 2015 - 10h - Amphi E. du Châtelet (médiathèque) - INSA Lyon

Titre :

Contribution to the design of switched-capacitor voltage regulators in 28nm FDSOI CMOS

Jury :

  • Directeur de thèse : ALLARD Bruno
  • Rapporteurs : COBOS José ; PRODIC Aleksandar
  • Examinateurs  : ELMBEYE Yves : HASBANI Frédéric ; LABBE Benoît ; TROCHUT Séverin

Résumé :

Mobile and multimedia devices offer more innovations and enhancements to satisfy user requirements. Chip manufacturers thus propose high performances SoC to address these needs. Unfortunately the growth in digital resources inevitably increases the power consumption while battery life-time does not rise as fast. Aggressive power management techniques such as dynamic voltage and frequency scaling have been introduced in order to keep competitive and relevant solutions. Nonetheless continuing in this direction involves more disruptive solutions to meet space and cost constraints. Fully integrated power supply is a promising solution. Switched-capacitor DC-DC converters seem to be a suitable candidate to keep compatibility with the manufacturing process of digital SoCs. This thesis focuses on the design of an embedded power supply architecture using switched-capacitor DC-DC converters.Addressing a large range of output power with significant efficiency leads to consider a multi-ratio power stage. With respect to the typical digital SoC, the input voltage is 1.8 V and the converter is specified to deliver an output voltage in the 0.3-1.2 V range. The reference voltage is varying according to typical DVFS requirements. A modular architecture accommodates the digital design flow where the flying capacitors are situated above the digital block to supply and the power switches are located as an external ring. Such an architecture offers high flexibility. Interleaving strategy is considered to mitigate the output voltage ripple. Such a converter admits the switching frequency as a control variable and linear regulation and hysteretic control are analyzed. A prototype has been fabricated in 28nm FDSOI technology by STMicroelectronics. A power density of 310 mW/mm2 is achieved at 72.5% peak efficiency with a silicon area penalty of 11.5% of the digital block area. The successful design methodology has been also applied to the design of a negative SC converter for body-biasing purpose in FDSOI. Simulation results demonstrate a strong interest for low power application.

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