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Home > Thèses et HDR > Thèses en 2013

16/07/2013 : Salam HAJJAR

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Salam HAJJAR soutient sa thèse le 16/07/2013 - 10h30 - Médiathèque de l’INSA de Lyon

Titre :

Conception sûre de systèmes embarqués à base de composants de commande sur étagère

Jury :

  • Directeur de thèse : NIEL Eric
  • Co-encadrant : DUMITRESCU Emil
  • Rapporteurs : FABIAN Martin ; PETIN Jean-François
  • Examinateurs : ALLA Hassane ; TOGUYENI Armand

Résumé :

This thesis provides a semi-formal verification method to help the control-command systems’ designers build a safe by construction systems. The work has an industrial context “FerroCOTS project” it focuses on the embedded systems’ design, with applications to the train control systems at Bombardier. The results presented rely on a series of choices: design method and underlying techniques, design constraints, as well as physical platform constraints, for the final implementation.
The work discusses the problem confronted during the design based on COTS and proposes a solution using the available methods; The Discrete controller synthesis and the Formal verification technique. The proposed method profits of each technique to facilitate the work of the designer and to fill gap around the other technique, i,e. the Model checking detects automatically the design errors and provides the discrete controller synthesis technique with a set of required inputs and the discrete controller synthesis method correct the detected errors instead of manually correcting them by the designer.
We argue that, a fully automatic detection and correction or design errors is not enough to valid a critical system, where any mistake can cost the life of a human-being or in the best cases a huge amount of money to correct such error. Thus, since the simulation of hardware systems exist, we profit of it, and we reassure the designer with a human-eyed satisfaction of the final system before implementing it in the physical environment.

The method contains 5 steps (1. Modelization, 2. error detection, 3. error correction, 4. final system verification, 5. simulation and validation) each step can only do a partial mission for the safety of the final system, and all together provide a safe system, free of errors and ready to be implemented on a chip like FPGA.

The motivation of our work is to provide a designer of control-command system with a semi-automatic method that can take advantages of the existing design assistant methods, to facilitate the designer’s job as possible. We aim also to present the DCS method to the domain of real systems, and see how far it can go in real life and where is it limited.

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