Nos tutelles

CNRS Ecole Centrale de Lyon Université de Lyon Université Lyon 1 INSA de Lyon

Nos partenaires



Accueil > Thèses et HDR > Thèses en 2013

10/07/2013 : Philipp RITTER

publié le , mis à jour le

Philipp RITTER a soutenu sa thèse le 10 juillet 2013 - INSA de Lyon

Titre :

Design and Optimization of High Speed Flash Analog-to-Digital Converters
in SiGe BiCMOS technologies

Jury :

  • Directeurs de thèse : Bruno ALLARD ; Michael MÖLLER
  • Rapporteurs : Hassan ABSOUSHADY ; Manfred BERROTH
  • Examinateurs : Jose Luis GONZALEZ ; Sébastien PRUVOST ; Eric TOURNIER

Résumé :

Integrated circuits realized in SiGe-bipolar technologies have a reputation for operating at very high speed but being very power consuming whereas circuits in the latest CMOS technology nodes are expected to operate at slightly lower speed but to consume signif icantly less power.
At low speed, the superiority of the Complementary- MOS topology in terms of power consumption is commonly accepted. At medium to high speed however, the Complementary - MOS topology has poor electrical performance such that paralleliz ation concepts following the divide and conquer concept have been developed to relax the high speed requirements on the circuitry. Not only do these concepts usually lead to an overhead in complexity and chip size but they also require supplementary circuitry for calibration and synchronization, which additionally affects the development time adversely. By contrast, bipolar technologies in conjunction with a ifferentially operated symmetrical circuit topology like the Current Mode Logic (CML) have highest speed potential. To take advantage thereof typically little or no parallelization is used in bipolar circuits. This usually keeps the complexity low, requires little overhead for auxiliary circuits and leads to puristic designs.
These two approaches aiming at a steady increase of the operating speed of integrated circuits become considerably apparent in the design of high speed analog-to-digital converters (ADC). This thesis provides design considerations for a high speed flash type ADC in Si Ge BiCMOS technologies, which after review of the state of the art turns out to be the ADC type suited best to benefit from the inherent high speed potential of bipolar circuits. It is the objective of this thesis to demonstrate that by adequately desig ning the ADC building blocks high speed operation throughout the ADC is possible, with a power efficient direct conversion scheme without any track-and-hold or time interleaving. In this context dealt with in detail are among others the widely passivehigh speed signal distribution over differential microstrip line tree structures, the dynamic linearity of emitter followers used as a linear input buffer for the high speed signal, or the bandwidth and linearity requirements of the comparators for high timing accuracy in the high speed signal magnitude detection. As a demonstrator the IC design of a 20 GS/s 6 bit track-and-hold less flash ADC in BiCMOS production technology is presented. For the high speed measurement a chip -on-module mounting technique is described, that is based on wirebonding and a dedicated high frequency polymeric substrate.